Oh, in that case, I think you're already running out of spec., unless you're overclocking the RP2040 to 360 MHz:...
The FT232H is the master in this case, my rp2040 is the slave. I have measured the clock with my Saleae logic pro 16 and it is roughly 30MHz.
...
(SSPCLK = clk_peri, SSPCLKIN = clock provided by an attached master)In the slave mode of operation, the SSPCLKIN signal from the external master is double-synchronized and then delayed
to detect an edge. It takes three SSPCLKs to detect an edge on SSPCLKIN. SSPTXD has less setup time to the falling
edge of SSPCLKIN on which the master is sampling the line.
The setup and hold times on SSPRXD, with reference to SSPCLKIN, must be more conservative to ensure that it is at the
right value when the actual sampling occurs within the SSPMS. To ensure correct device operation, SSPCLK must be at
least 12 times faster than the maximum expected frequency of SSPCLKIN.
Statistics: Posted by carlk3 — Tue Sep 10, 2024 11:26 pm