Reading the RP3250 datasheet, I see nothing preventing these voltage level combinations for RP2350 power domains:
IOVDD=1.8V
QSPI_IOVDD=1.8V
USB_OTP_VDD =3.3V
Or this one:
IOVDD=1.8V
QSPI_IOVDD=3.3V
USB_OTP_VDD =3.3V
Or did I miss something? If QSPI_IOVDD is 1.8V could it have issues booting from flash?
For context, the reason IOVDD is 1.8V is because the RP2350 interfaces with an FPGA with max 1.8V LVCMOS IOs.
Second related question. I have a couple of choices for ADC_AVDD. If ADC_AVDD is 3.3V, in either of the combinations given above, I lose almost 1 bit of ADC precision, because the ADC capable pins must not exceed IOVDD+0.5. Alternatively, I could make ADC_AVDD 1.8V but, as the datasheet notes, "the performance of the ADC will be compromised at voltages below 2.97 V". If IOVDD must be 1.8V, which is the better level for ADC_AVDD?
IOVDD=1.8V
QSPI_IOVDD=1.8V
USB_OTP_VDD =3.3V
Or this one:
IOVDD=1.8V
QSPI_IOVDD=3.3V
USB_OTP_VDD =3.3V
Or did I miss something? If QSPI_IOVDD is 1.8V could it have issues booting from flash?
For context, the reason IOVDD is 1.8V is because the RP2350 interfaces with an FPGA with max 1.8V LVCMOS IOs.
Second related question. I have a couple of choices for ADC_AVDD. If ADC_AVDD is 3.3V, in either of the combinations given above, I lose almost 1 bit of ADC precision, because the ADC capable pins must not exceed IOVDD+0.5. Alternatively, I could make ADC_AVDD 1.8V but, as the datasheet notes, "the performance of the ADC will be compromised at voltages below 2.97 V". If IOVDD must be 1.8V, which is the better level for ADC_AVDD?
Statistics: Posted by alastairpatrick — Thu Jan 09, 2025 6:42 pm