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Device Tree • Re: RPI5: Issue with GPCLK0 Clock Generation on GPIO4 in ALT0 Mode

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Good that it works, but you'll probably find it has suboptimal performance as the divisor will be toggling between /8 and /9. Support for arbitrary I2S master-mode clocks has now been merged[1] so regular rpi-update will get you the ability to use clocks derived directly from pll_audio, but only on I2S SCLK pins.

[1] https://github.com/raspberrypi/linux/pull/5999

Statistics: Posted by jdb — Mon Mar 11, 2024 5:04 pm



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