there are ~3 different things affecting the max baud rate for the PL011
first, its based around 16x over-sampling, so internally, it has to generate a clock that is 16x your baud
taking your 4mbaud figure as an example, that means it has to generate a 64mhz clock for the oversampling
internally, the PL011 will divide a reference clock by a configured amount, to generate that 64mhz clock
this shows that the uart reference clock is 48mhz, so 4mbaud is a fail in this configuration
so, that uart ref-clock is the first limit, 48mhz/16, 3mbaud, is the max the uart can do
but, you can always use init_uart_clock=64000000 in config.txt to raise that refclk, and go beyond!!
the next problem i can think of, is fractional division
if you take a 48mhz refclk, and try to generate a 40mhz clock, then you need 48mhz/1.2
the PL011 will just semi-randomly switch between 48mhz/1 and 48mhz/2 (48mhz and 24mhz), such that the average clock is the desired 40mhz
with such a large difference, that will cause jitter, but it sort of gets averaged out over 16 samples
you can improve this by either using a refclk that is a multiple of your desired clock, or just a faster ref clk
(but, then you have the same problem one level up, the uart refclk is just fractional division of plld_per)
and then the third problem, what clock is the transistors in the PL011 actually rated for?
how quickly can the gpio pin swing?
at what point will the uart just malfunction, even if it had perfect timing
first, its based around 16x over-sampling, so internally, it has to generate a clock that is 16x your baud
taking your 4mbaud figure as an example, that means it has to generate a 64mhz clock for the oversampling
internally, the PL011 will divide a reference clock by a configured amount, to generate that 64mhz clock
Code:
root@raspberrypi:/sys/kernel/debug/clk# cat /proc/cpuinfo ...Hardware : BCM2835Revision : 000eSerial : 00000000230aad04Model : Raspberry Pi Model B Rev 2root@raspberrypi:/sys/kernel/debug/clk# cat clk_summary enable prepare protect duty clock count count count rate accuracy phase cycle--------------------------------------------------------------------------------------------- osc 6 6 1 19200000 0 0 50000 plld 3 3 0 2000000024 0 0 50000 plld_per 2 2 0 500000006 0 0 50000 uart 1 2 0 47999625 0 0 50000so, that uart ref-clock is the first limit, 48mhz/16, 3mbaud, is the max the uart can do
but, you can always use init_uart_clock=64000000 in config.txt to raise that refclk, and go beyond!!
the next problem i can think of, is fractional division
if you take a 48mhz refclk, and try to generate a 40mhz clock, then you need 48mhz/1.2
the PL011 will just semi-randomly switch between 48mhz/1 and 48mhz/2 (48mhz and 24mhz), such that the average clock is the desired 40mhz
with such a large difference, that will cause jitter, but it sort of gets averaged out over 16 samples
you can improve this by either using a refclk that is a multiple of your desired clock, or just a faster ref clk
(but, then you have the same problem one level up, the uart refclk is just fractional division of plld_per)
and then the third problem, what clock is the transistors in the PL011 actually rated for?
how quickly can the gpio pin swing?
at what point will the uart just malfunction, even if it had perfect timing
Statistics: Posted by cleverca22 — Thu Apr 11, 2024 10:42 pm